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The badass tutorial for creating makefiles!

Tutorial 4: basic targets 2

In this step i will continue on how to use targets

In this tutorial just copy or reuse the files and folder from the previous tutorial.

Change the contents of the makefile to this:

#Another simple makefile.

CC = gcc
PROGRAM = prog

all: $(PROGRAM)

$(PROGRAM): $(PROGRAM).o
	$(CC) $< -o $@

$(PROGRAM).o: $(PROGRAM).c
	$(CC) $< -c -o $@

run: all
	./$(PROGRAM)
	
clean:
	rm $(PROGRAM).o

$@ and $< is two variables which will change depending on the target.

Note also the you can write a variable in several ways, such as $@ or $(@) or ${@}.

Lots of new stuff!

Its quite tricky to see whats happening!

In order to understand that, its quite good to understand how a target and its recipies (commands) work. The general rule is:

target: dependencies
[tab]	recipie/command

So if you for example run:

make run

This will run several targets.

The result after running make run should be:

gcc prog.c -c -o prog.o
gcc prog.o -o prog
./prog
Hello World!

A tip is to run:

make [target] -n -B

It will run the entire chain no matter what. This may be useful for debugging purposes.

Common targets

You probably saw that i also added the target clean. Clean is a common target for cleaning up your build, so if you get stuck somewhere it might be a simple solution to just add it there.

For now its good to know the targets all and clean

The complete list of common targets: link

See also:

Last modified: 13 September 2016 22:19:13. | CaF2 © (All rights reserved)